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d a t a sh eet product speci?cation supersedes data of 1998 aug 18 file under integrated circuits, ic02 2000 feb 21 integrated circuits tda8006 multiprotocol ic card coupler
2000 feb 21 2 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 features 80c52 core with 16 kbyte rom and 256 byte ram extra 1 kbyte ram outside the core for data storage control and communication through a standard rs232 full duplex interface or a parallel interface specific iso 7816 uart with parallel access on i/o for automatic convention processing, variable baud rate through frequency or division ratio programming, error management at character level for t = 0, extra guard time register v cc generation (5 v 5% or 3 v 5%, 65 ma maximum with controlled rise and fall times) card clock generation (up to 10 mhz) with two times synchronous frequency doubling card clock stop high, clock stop low or 1.25 mhz (from internal oscillator) for card power-down mode clkout output for clocking external devices with either f xtal , 1 2 f xtal or 1 4 f xtal automatic activation and deactivation sequence through an independent sequencer supports the asynchronous protocols t = 0 and t = 1 in accordance with iso 7816, europay, mastercard and visa (emv) supports synchronous cards short circuit current limiting special circuitry for killing spikes during power-on or off supply supervisor for power-on/off reset step-up converter (supply voltage from 4.2 to 6 v) power-down and sleep mode for low power consumption enhanced esd protection on card side (6 kv minimum) software library for easy integration within the application. applications smart card readers for multiprotocol applications (emv banking, digital pay tv, access control, etc.). general description it is assumed that the reader of this data sheet is familiar with iso 7816. the tda8006 is controlled either through a standard serial interface or a parallel bus, it takes care of all iso 7816, emv and gsm11.11 requirements. it gives the card and the set a very high level of security due to its special hardware against esd, short circuit, power failure, etc. its integrated step-up converter allows operation within a supply voltage range of 4.2 to 6 v. a special version of the tda8006 is available which has its internal connections to the controller accessible through external pins. this allows easy development and evaluation when used with a 80cl580 microcontroller or a development tool. an emulation board is available. a software library has been developed, taking care of all actions required for t = 0, t = 1 and synchronous protocols. this library may be either linked with the application software before masking, or masked in the internal rom (see application note an98106 ). ordering information type number package name description version tda8006h/c1 qfp64 plastic quad ?at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm sot319-2 tda8006h/c2 tda8006h/c3 tda8006ah/c1 qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 tda8006ah/c2 tda8006ah/c3
2000 feb 21 3 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 quick reference data note 1. i dd in all configurations include the current at pins v dd , v dda and v ddram . symbol parameter conditions min. typ. max. unit v dd supply voltage 4.2 - 6v i dd(pd) supply current in power-down mode v dd = 5 v; card inactive; note 1 -- 250 m a i dd(sm) supply current in sleep mode card powered but clock stopped; note 1 -- 1500 m a v cc card supply voltage including static loads (5 v card) 4.75 5.0 5.25 v with 40 nas dynamic loads on 100 nf capacitor (5 v card) 4.6 - 5.4 v including static loads (3 v card) 2.80 - 3.20 v with 24 nas dynamic loads on 100 nf capacitor (3 v card) 2.75 - 3.25 v i cc card supply current operating -- 65 ma overload detection - 80 - ma sr slew rate (rise and fall) maximum load capacitor pin v cc 400 nf (including typical 100 nf decoupling) 0.10 0.16 0.22 v/ m s t de deactivation cycle duration -- 100 m s t act activation cycle duration -- 225 m s f xtal crystal frequency 4 - 25 mhz f oper operating frequency external frequency applied on pin xtal1 0 - 25 mhz t amb operating ambient temperature - 25 - +85 c
2000 feb 21 4 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 block diagram handbook, full pagewidth mgr225 63, 64, 1 to 6 (43, 44, 1, 2) (2) 19 to 12 (11 to 8) (1) 58 (38) 59 (39) 60 (40) 53 (35) 54 (36) tda8006h (tda8006ah) 6 8 p40 to p47 microcontroller 80c52 16-kbyte rom 256-byte ram analog drivers and sequencer p20 to p27 p00 to p07 p30/rxd p31/txd p33/int1 p10/t2 p11/t2ex 23 (14) v ddram 24 (15) gndram 43 (30) clkout 7 (3) 8 (4) 61 (41) 11 (7) 62 (42) psen 52 (34) reset 44 (31) cdelay 45 (32) alarm ale p36/wr p37/rd (22) 32 (26) 39 vup c8 (25) 38 c4 (17) 27 clk (16) 26 rst (23) 36 v cc (24) 37 i/o (29) 42 pres xtal2 9 (5) k0 to k3 48 to 51 (3) xtal1 10 (6) supply and supervisor 1024 aux ram peripherals clock circuitry port extension t = 0,1 iso uart internal oscillator ea int0 step-up converter c4 gnd s1 s2 p34 c8 i/o off 3 v/5 v cmdvcc p35 v dd 100 nf 100 nf 100 nf 31 (21) 29 (19) 41(28) 40 (27) agnd v dda 30 (20) 28 (18) fig.1 block diagram. minimum value for capacitor between v dda and agnd is 2.2 m f. pin numbers in parenthesis represent the tda8006ah. (1) ports p04 to p07 not applicable for qfp44 package. (2) ports p24 to p27 not applicable for qfp44 package. (3) ports k0 to k3 not applicable for qfp44 package.
2000 feb 21 5 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 pinning symbol pin description qfp64 qfp44 p22 1 1 address 10/general purpose i/o port p23 2 2 address 11/general purpose i/o port p24 3 - address 12/general purpose i/o port p25 4 - address 13/general purpose i/o port p26 5 - address 14/general purpose i/o port p27 6 - address 15/general purpose i/o port psen 7 3 program store enable output ale 8 4 address latch enable xtal2 9 5 crystal connection xtal1 10 6 crystal connection or external clock input ea 11 7 external access p07 12 - address/data 7/general purpose i/o port p06 13 - address/data 6/general purpose i/o port p05 14 - address/data 5/general purpose i/o port p04 15 - address/data 4/general purpose i/o port p03 16 8 address/data 3/general purpose i/o port p02 17 9 address/data 2/general purpose i/o port p01 18 10 address/data 1/general purpose i/o port p00 19 11 address/data 0/general purpose i/o port n.c. 20 12 not connected n.c. 21 13 not connected n.c. 22 - not connected v ddram 23 14 supply voltage for the auxiliary ram gndram 24 15 ground for the auxiliary ram n.c. 25 - not connected rst 26 16 card reset output (iso contact c2) clk 27 17 clock output to the card (iso contact c3) agnd 28 18 ground for the analog part s1 29 19 contact 1 for the step-up converter (a ceramic capacitor of 100 nf must be connected between s1 and s2) v dda 30 20 analog supply voltage for the voltage doubler s2 31 21 contact 2 for the step-up converter (a ceramic capacitor of 100 nf must be connected between s1 and s2) vup 32 22 output of the step-up converter; must be decoupled with a 100 nf ceramic capacitor n.c. 33 - not connected n.c. 34 - not connected n.c. 35 - not connected v cc 36 23 card supply output voltage (iso contact c1)
2000 feb 21 6 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 i/o 37 24 data line to/from the card (iso contact c7) c4 38 25 auxiliary i/o for iso contact c4 (synchronous cards for example) c8 39 26 auxiliary i/o for iso contact c8 (synchronous cards for example) gnd 40 27 ground v dd 41 28 supply voltage pres 42 29 card presence contact input (active high or low by mask option); see table 12 clkout 43 30 output for clocking external devices cdelay 44 31 external capacitor connection for delayed reset signal alarm 45 32 open drain reset output (active high or low by mask option); see table 12 test 46 33 test pin (must be left open-circuit in the application) inhib 47 - test pin (must be left open-circuit in the application) k0 48 - output port from port extension ( 2 ma push-pull) k1 49 - output port from port extension ( 2 ma push-pull) k2 50 - output port from port extension ( 2 ma push-pull) k3 51 - output port from port extension ( 2 ma push-pull) reset 52 34 input for resetting the microcontroller (active high) p10/t2 53 35 general purpose i/o port (connected to p10) p11/t2ex 54 36 general purpose i/o port (connected to p11) n.c. 55 37 not connected n.c. 56 - not connected n.c. 57 - not connected p30/rxd 58 38 general purpose i/o port or serial interface receive line p31/txd 59 39 general purpose i/o port or serial interface transmit line p33/ int1 60 40 general purpose i/o port or interrupt (connected to p33) p36/ wr 61 41 general purpose i/o port or external data memory write strobe p37/ rd 62 42 general purpose i/o port or external data memory read strobe p20 63 43 address 8/general purpose i/o port p21 64 44 address 9/general purpose i/o port symbol pin description qfp64 qfp44
2000 feb 21 7 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 handbook, full pagewidth tda8006h mgr226 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p22 p23 p24 p25 p26 p27 ale p07 p06 p05 p04 xtal2 xtal1 k3 k2 k1 k0 inhib test alarm cdelay n.c. n.c. n.c. 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 n.c. n.c. n.c. n.c. n.c. n.c. v ddram gndram n.c. clkout v dd gnd c8 c4 i/o p03 p02 p00 v cc psen pres p20 p31/txd p30/rxd p11/t2ex p10/t2 reset p21 rst clk agnd v dda s2 vup p01 s1 ea p33/int1 p36/wr p37/rd fig.2 pin configuration (qfp64).
2000 feb 21 8 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 tda8006ah mgr227 test alarm cdelay clkout v dd gnd c8 c4 i/o v cc p22 p23 psen ale xtal2 xtal1 p03 p02 p00 pres p20 p37/rd p36/wr p33/int1 p31/txd p30/rxd p11/t2ex p10/t2 reset p21 n.c. n.c. v ddram gndram rst clk agnd v dda s2 vup n.c. s1 ea p01 fig.3 pin configuration (qfp44).
2000 feb 21 9 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 functional description microcontroller the microcontroller is an 80c52 with 16 kbytes of rom, 256 byte ram, timers 0, 1, 2 , and 5 i/o ports (port p0: open-drain; ports p1 to p3: weak pull-up). port p4 is identical to 83ce560, except that precharge circuits ensure fast rise times at end of read mode (transition times <0.5 m s). the rom code content can be tested by signature to avoid reading it out after masking; for security bit option, see table 12. the cpu, timers 0 and 1, serial uart, parallel i/o ports, 256 byte ram, 16 kbyte rom and external bus are conventional c51 family library elements. timer 2 is a conventional c52 element (interrupt enable bit et2: bit 3 in register ien1 at byte address e8h and interrupt priority bit pt2: bit 3 in register ip1 at byte address f8h. register pcon has an added feature: pcon.5 = rfi (reduced radio frequency interference bit). when set to logic 1, pin ale cannot be toggled. ale clears on reset. if access is required to the external data memory via movx instructions (see table 1), set bit pcon.6 = ard in the pcon register to logic 1. for further information, please refer to the published specification of the 83ce560 in data handbook ic20; 80c51-based 8-bit microcontrollers . ports p40 to p47, int0 and p12 to p17 are used internally for controlling the smart card interface and the other peripherals. ports p34 and p35 are used to control the auxiliary contacts c4 and c8. the list of differences given in table 1 may help the software developer of the dedicated emulation board for the tda8006 or other devices. table 1 list of differences between tda8006, ce560, cl580 and c52 features tda8006 83ce560 cl580 intel c52 p4 address c0 c0 c1 no timer 2 intel philips intel intel rom size 16 kbytes 64 kbytes 6 kbytes 8 kbytes external 0 interrupt vector 0003h 0003h 0003h 0003h external 0 interrupt priority highest (1st) highest (1st) highest (1st) highest (1st) timer 0 interrupt vector 000bh 000bh 000bh 000bh timer 0 interrupt priority 2nd 2nd 4th 2nd external 1 interrupt vector 0013h 0013h 0013h 0013h external 1 interrupt priority 3th 3th 7th 3th timer 1 interrupt vector 001bh 001bh 001bh 001bh timer 1 interrupt priority 4th 4th 10th 4th serial 0 interrupt vector 0023h 0023h 0023h 0023h serial 0 interrupt priority 5th 5th 13th 5th timer 2 interrupt vector 004bh 0033h, etc. (8) 0033h 002bh timer 2 interrupt priority lowest (6th) miscellaneous 5th lowest (6th) i 2 c-bus no yes yes no adc no yes yes no 32 khz oscillator no yes no no pwm no yes yes no watchdog no yes yes no interrupts on p1 no no yes no additional ram 1 kbyte peripheral 2 kbyte movx no no wake-up from power-down mode reset, int0, int1 reset, int0, int1 + other reset, int2 to i nt8 reset
2000 feb 21 10 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 table 2 special function register bit addresses x = dont care. register byte address (hex) bit address [hex] bit reset value bit function msb lsb ip1 f8 [ff] [fe] [fd] [fc] [fb] [fa] [f9] [f8] ---- pt2 --- xxxx 0xxx b f0 [f7] [f6] [f5] [f4] [f3] [f2] [f1] [f0] -------- 0000 0000 ien1 e8 [ef] [ee] [ed] [ec] [eb] [ea] [e9] [e8] ---- et2 --- 0000 0000 acc e0 [e7] [e6] [e5] [e4] [e3] [e2] [e1] [e0] -------- 0000 0000 psw d0 [d7] [d6] [d5] [d4] [d3] [d2] [d1] [d0] cy ac f0 rs1 rs0 ov f1 p 0000 0000 t2con c8 [cf] [ce] [cd] [cc] [cb] [ca] [c9] [c8] tf2 exf2 rclk tclk exen2 tr2 c/t2n cp/rl2n 0000 0000 p4 c0 [c7] [c6] [c5] [c4] [c3] [c2] [c1] [c0] -------- 1111 1111 ip0 b8 [bf] [be] [bd] [bc] [bb] [ba] [b9] [b8] --- ps0 pt1 px1 pt0 px0 xxx0 0000 p3 b0 [b7] [b6] [b5] [b4] [b3] [b2] [b1] [b0] -------- 1111 1111 ien0 a8 [af] [ae] [ad] [ac] [ab] [aa] [a9] [a8] ea -- es0 et1 ex1 et0 ex0 0xx0 0000 p2 a0 [a7] [a6] [a5] [a4] [a3] [a2] [a1] [a0] -------- 1111 1111 scon 98 [9f] [9e] [9d] [9c] [9b] [9a] [99] [98] sm0 sm1 sm2 ren tb8 rb8 ti ri 0000 0000 p1 90 [97] [96] [95] [94] [93] [92] [91] [90] -------- 1111 1111 tcon 88 [8f] [8e] [8d] [8c] [8b] [8a] [89] [88] tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 0000 0000 p0 80 [87] [86] [85] [84] [83] [82] [81] [80] -------- 1111 1111
2000 feb 21 11 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 table 3 other register byte addresses supply the circuit operates within a supply voltage range of 4.2 to 6 v. the supply pins are v dd , v dda , gnd, agnd, v ddram and gndram. pins v dda and agnd supply the card analog drivers and have to be externally decoupled because of the large current spikes that the card and the step-up converter can create. v ddram and gndram supply the auxiliary ram and should be decoupled separately. v dd and gnd supply the rest of the chip. an integrated spike killer ensures the contacts to the card remain inactive during power-up or power-down. an internally generated voltage reference is used by the step-up converter, the voltage supervisor and the v cc generator. if v dd is too low to ensure proper operation, the voltage supervisor generates an alarm pulse, whose length is defined by an external capacitor tied to the cdelay pin, (1 ms per 1 nf typical). this pulse is used to reset the controller and is used in parallel with an external reset input which can come from the system controller. it is also used to either block any spurious on-card contacts during a controller reset or to force an automatic deactivation of the contacts in the event of supply drop-out (see sections activation sequence and deactivation sequence). it is also fed to an external open-drain output (called alarm) which can be chosen active high or low by mask option (see table 12). step-up converter except for the v cc generator and the other card contact buffers, the whole circuit is powered by v dd , v dda and v ddram . if the supply voltage is 4.2 v, then a higher voltage is needed for the supply to the iso contacts. when a card session is requested by the controller, the sequencer first starts the step-up converter. this uses switched capacitors which are clocked at a frequency of approximately 2.5 mhz by an internal oscillator. the output voltage vup is regulated at approximately 6 v and then fed to the v cc generator. v cc and gnd are used as a reference for all other card contacts. register byte address (hex) bit reset value sp 81 0000 0111 dpl 82 0000 0000 dph 83 0000 0000 pcon 87 0000 0000 tmod 89 0000 0000 tl0 8a 0000 0000 tl1 8b 0000 0000 th0 8c 0000 0000 th1 8d 0000 0000 s0buf 99 xxxx xxxx rcap2l ca 0000 0000 rcap2h cb 0000 0000 tl2 cc 0000 0000 th2 cd 0000 0000 handbook, full pagewidth mgr228 v th(vdd) v dd v th(cdelay) cdelay alarm t w fig.4 voltage supervisor.
2000 feb 21 12 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 iso 7816 security the correct sequence during activation and deactivation of the card is ensured by a specific sequencer clocked at a frequency which is a division ratio of the internal oscillator. activation (bit cmdvcc within the ports extension register high) is only possible if the card is present (pin pres high or low according to the mask option) and if the supply voltage is correct (alarm signal inactive). the presence of the card is signalled to the controller by the off bit (within the uart status register), generating an interrupt, if enabled, when toggling. during a session, the sequencer performs an automatic emergency deactivation in the event of card take-off, supply voltage drop or short circuit. the off bit goes low, thereby warning the controller through the interrupt line int0 and the status register. peripheral interface (see figs 5 and 6) this block allows parallel communication with the four peripherals (iso 7816 uart, clock generator, on/off sequencer and auxiliary ram) through an 8-bit data bus, 6-bit address and control bus and one interrupt line to the controller. the data bus consists of ports p40 (data bit 0) to p47 (data bit 7). the address bus consists of ports ad0 (p12), ad1 (p13), ad2 (p14) and ad3 (p15). the control lines are r/ w (p16) and en (p17). the interrupt line is int0. during a read operation, en goes low allowing the controller to read data on the bus. during a write operation, the data should be present on the bus before asserting en low which allows the data to be written to the registers. after resetting en high, the controller must release the bus by setting port p4 high again (the transition times on port p4 are less than 500 ns). the interrupt line is reset high when reading out the status register. r ead operation set port p4 to ffh select the register with ad0, ad1, ad2, ad3 assert r/ w high assert en low; the data is available on data bus p4 read the data on port p4 set en high; the bus is set to high impedance. w rite operation select the correct register with ad0, ad1, ad2, ad3 assert r/ w low write data to the data bus port p4 assert en low; the data is written to the register set en high set port p4 to ffh; the bus is set to high impedance. integrated precharges allow fast rising edges on port p4 when changing from read mode to write mode, thus avoiding the need to trigger the active pull-ups on port p4. handbook, full pagewidth mgr229 p4 xx ff ff ff data r/w ad0 to ad3 x ad ad read data cycle write data cycle en data fig.5 use of peripheral interface.
2000 feb 21 13 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgr230 8 8 transmit register receive register status register synchronous in register synchronous out register guard time register configuration register iso 7816 uart int en r/w ad3 ad2 ad1 ad0 low address register high address register memory read register memory write register auxiliary ram en r/w ad3 ad2 ad1 ad0 peripheral extension register on/off sequencer interface, security and power control en r/w ad3 ad2 ad1 ad0 clock configuration register programmable divider clock generator en r/w ad3 ad2 ad1 ad0 micro clock uart clock card clock external clock xtal i/o c4 c8 k0 k1 k2 k3 cmdvcc rst det err por clk clkout oscint xtal1 80c52 core p17 p00/p07 8 p20/p27 ale p32/int0 p15 p14 p13 p12 p40 to p47 p34 p35 p16 osc reset databus control bus psen ea p37/rd p36/wr p33/int1 p30/rxd p31/txd p10/t2 p11/t2ex fig.6 peripheral interface.
2000 feb 21 14 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 table 4 register addresses x = dont care. ad3 ad2 ad1 ad0 r/ w register peripheral 00000 ccr (clock con?guration register) clock generator 00010 pdr (programmable divider register) 00110 sor (synchronous output register) iso 7816 uart 00111 sir (synchronous input register) 01000 utr (uart transmit register) 01001 urr (uart receive register) 01011 usr (uart status register) 01010 ucr (uart con?guration register) 01100 gtr (guard time register) 01110 per (ports extension register) on/off sequencer 1 1 0 x 0 mar0 (memory address low) auxiliary ram 1 1 1 x 0 mar1 (memory address high) 1 0 0 x 0 mwr (memory write register) 1 0 0 x 1 mrr (memory read register) clock circuit the microcontroller clock (osc), the card clock (clk), the iso 7816 uart clock, and the clock to the external world (clkout), are derived from the main clock signals (xtal from 4 to 20 mhz, or an external clock signal applied to xtal1), or the internal oscillator (f int ). microcontroller clock (osc): after power-on or reset, the microcontroller is clocked at 1 8 f int . then, the application may decide to clock it at 1 2 f int , 1 2 f xtal or f xtal . all frequency changes are synchronous, thereby ensuring no hang-up due to short spikes etc. card clock (clk): the application may send a clock frequency of 1 2 f xtal , 1 4 f xtal , 1 8 f xtal or 1 2 f int ( ? 1.25 mhz), or may stop the clock at high or low. all transitions are synchronous, ensuring correct pulse length during start or change, in accordance with iso 7816. after power-on or reset, clk is held low. external clock output (clkout): clkout is a permanent clock output for external use. the following frequencies are possible: f xtal , 1 2 f xtal and 1 4 f xtal . all transitions are synchronous. after power-on or reset, clkout is fixed at 1 4 f xtal . iso 7816 uart clock: the clock to the iso 7816 uart is identical to the clock to the card (clk). to achieve the different i/o baud rates as defined by values f and d (see table 7), the clock signal is counted by an auto-reload 8-bit programmable counter and then divided by a 31 or 32 prescaler. all these configurations are controlled by the clock configuration register and by the programmable divider register.
2000 feb 21 15 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 table 5 clock con?guration register (ccr; address 0; write only; all bits cleared after reset) x = dont care. d7 d6 d5 d4 d3 d2 d1 d0 uart prescaler clk clkout osc xxxxxxx0 ? 31 xxxxxxx1 ? 32 xxxx0 0 0x stoplow xxxx0 0 1x 1 2 f xtal xxxx0 1 0x 1 4 f xtal xxxx0 1 1x 1 8 f xtal xxxx1 0 0x 1 2 f int xxxx1 0 1x stop high xx0 0xxxx 1 4 f xtal xx0 1xxxx f xtal xx1 0xxxx 1 2 f xtal 0 0xxxxxx 1 8 f int 0 1xxxxxx f xtal 1 0xxxxxx 1 2 f xtal 1 1xxxxxx 1 2 f int the hexadecimal value stored in the programmable divider register (pdr) is the auto-reload value of an 8-bit counter clocked by the card clock (clk); when the value is loaded in the counter, it counts from this value till overflow; then it is reloaded with the same value and the count restarts. the output of the counter is then divided by 31 or 32 depending on the programmed value of the uart prescaler. the result is the iso 7816 uart clk which is used for shifting the data in or out on the i/o line. the example shown in fig.7 shows how to program a division factor of 372. with these registers, the baud rates given in table 7 are achieved according to iso 7816. the division ratio of 31 or 32 depends on which prescaler is selected, and the hexadecimal value is the value programmed within the pdr. table 6 programmable divider register (pdr; address 1; write only; all bits cleared after reset) note 1. a division factor of f4h, for example, would be 1111 0100 reading from d7 to d0. d7 d6 d5 d4 d3 d2 d1 d0 division factor n7 n6 n5 n4 n3 n2 n1 n0 n7n6n5n4 n3n2n1n0 (1)
2000 feb 21 16 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 handbook, full pagewidth mgr231 8-bit auto-reload counter with pdr = f4h clk ? 31 ? 32 iso 7816 uart clk fig.7 baud rate selection on i/o. table 7 selecting baud rate using f and d values baud rate is selected by values d and f shown in parenthesis. the pdr is loaded with a value shown in hexadecimal, and either prescaler 31 or 32 is selected. [value d] pdr value prescaler ? 31 prescaler ? 32 [value f] [value f] [0000] [0001] [0010] [0011] [0100] [0101] [0110] [1001] [1010] [1011] [1100] [1101] [0001] f4 f4 ee e8 dc d0 c4 f0 e8 e0 d0 c0 [0010] fa fa f7 f4 ee e8 e2 f8 f4 f0 e8 e0 [0011] fd fd - fa f7 f4 f1 fc fa f8 f4 f0 [0100] --- fd - fa - fe fd fc fa f8 [0101] ----- fd - ff - fe fd fc [0110] --------- ff - fe [1000] ff ff - fe fd fc fb - fe - fc - [1001] ------ fd -----
2000 feb 21 17 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 on/off controller table 8 on/off controller bits (per; address 7; write only; all bits cleared after reset) bit name description d0 cmdvcc; set and reset by software set to 1 for starting activation sequence of the card, and reset to 0 for starting deactivation d1 rstin; set and reset by software control line rst for card contact c2 in manual mode (active high) d2 force inverse parity (fip); set and reset by software when low, the uart processes the parity according to iso 7816; when high, the uart processes the inverse parity (which causes parity errors during transmission and not acknowledge signals during reception) d3 automatic atr processing enabling (atren); set by software, reset by hardware when high, the uart automatically counts the clock pulses during atr and controls the rst contact; this bit is automatically reset by hardware when a start bit is detected on i/o or when the card is declared as mute; when low, this automatic processing is disabled (manual mode) d4 k0; set and reset by software auxiliary 2 ma push-pull output control (inverted output) d5 k1; set and reset by software auxiliary 2 ma push-pull output control (inverted output) d6 k2; set and reset by software auxiliary 2 ma push-pull output control (inverted output) d7 k3; set and reset by software auxiliary 2 ma push-pull output control (inverted output) the on/off controller is used for activating or deactivating the card, for controlling contact c2 (rst) manually through rstin or automatically, for forcing inverse parity (for flow control or test purposes), and for controlling four independent push-pull output lines k0 to k3. after having cleared the iso 7816 uart reset bit (see uart configuration register) and checking the card presence within the status register, the software may initiate an activation sequence by setting bit cmdvcc high. it may also initiate a deactivation sequence by resetting this bit (see activation and deactivation sequences). the timings during the atr may be checked either manually (using rstin and t 3 /t 5 for counting clock pulses) or automatically by setting bit atren high (see section activation sequence). in this case, hardware controls both rst and the counting of clk pulses. bit atren is reset by hardware when a start bit has been detected before 2 40100 clk pulses for versions c2 and c3 (2 45000 clk pulses for version c1), or when the card is declared as mute. setting this bit high again during a session initiates a warm reset. a warm reset may also be done manually by using rstin and t 3 /t 5 again. iso 7816 uart the iso 7816 uart handles all specific requirements defined in iso 7816 t = 0 and t = 1 protocol types. it is also able to deal with synchronous cards (in conjunction with contacts c4 and c8). in addition, there is a possibility to force parity errors for test purposes or flow control. the counting of clk cycles during atr is possible by either hardware or software. the iso 7816 uart is configured with 2 registers: uart configuration register (ucr) and guard time register (gtr). when timings are given in terms of etu (elementary time unit as defined by iso 7816), then the reference is the negative edge of the start bit of the character being received or transmitted, unless otherwise specified.
2000 feb 21 18 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 table 9 uart con?guration register (ucr; address 5; write only; all bits cleared after reset) bit name description d0 reset iso 7816 uart (riun); set by software, reset by software when low, this bit resets the uart; must be set by software before any use of the uart d1 start session (ss); set by software, reset by software when high, this bit allows the detection of the convention during the initial character of the card; must be reset by software after correct reception of the ?rst character and before complete reception of the next character d2 last character to transmit (lct); set by software, reset by hardware or software when high, this bit allows automatic toggling from transmission to reception mode after successful transmission of the last character; in this case, trn is also reset by hardware d3 transmit/receive-n (trn); set by software, reset by software or hardware when low, the uart is in reception mode; when high, it is in transmission mode; int goes low when trn is set d4 not used d5 protocol selection (ps); set by software, reset by software when low, the uart is in t = 0 mode; when high, the uart is in t = 1 mode d6 3 v/5 v-n (tfn); set by software, reset by software when low, the card supply voltage v cc = 5 v; when high, v cc =3v d7 synchrone/asynchrone-n (san); set by software, reset by software when high, this bit allows direct monitoring of i/o by bit d0 of sir or sor; when low, i/o is fed to the iso 7816 uart r eception in order to start a session with the card, bit riun (which resets the iso 7816 uart when low) must be set high. the uart recognizes the convention (direct or inverse) of the characters received while bit ss (start session) is high. then the uart automatically converts any transmitted or received character according to this convention, so the software only has to deal with characters written in direct convention. indeed, bit ss must be reset by software after correct receipt of the first character of the atr (ts) and before complete receipt of the next character. reception mode is selected when trn is low. bit fsd is set within the uart status register (usr), and an interrupt is generated, if enabled, at the start bit of the received character when ss is high, allowing the manual clk count during atr. the interrupt will be cleared on the rising edge of en during the status read operation. for the next characters, bit rbf is set at 10.5 etu and an interrupt is generated, if enabled, to indicate that a character has been received, with or without parity error, and that this character may be read within the reception register. the interrupt is cleared on the falling edge of en during the read operation of the received character. in protocol type t = 0 (bit ps low), the i/o line is automatically pulled low between 10.5 and 11.75 etu if a character parity error is detected (parity error handling at character level). in protocol type t = 1 (bit ps high), if a parity error is detected, bit pe is set in the status register, but the i/o line is not pulled low.
2000 feb 21 19 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 handbook, full pagewidth mgr232 i/o ss riu cmdvcc p4 ff ff ff ff ff r/w en int fsd rbf release reset set start session set cmdvcc first start read status int cleared anything buffer full read status read character and int cleared reset start session 10.5 etu fig.8 first character reception. t ransmission transmission mode is selected when trn is high. if enabled, an interrupt occurs on the rising edge of trn, indicating that the transmission buffer is empty and ready to accept a character for transmission. the interrupt is cleared during the read status operation. the character is written to the utr on the falling edge of en during the write operation, and starts to be transmitted on the rising edge of en. the i/o line is read at 10.84 etu to check if the card has detected a parity error. at the same time, bit tbe is set in the usr, and, if enabled, an interrupt occurs to indicate that the transmission buffer is empty, and that a new character may be written. if the parity is correct, the transmission of the next character will start at 12 etu + gt + 0.5 etu after the start bit of the previous character (see section extra guard time). if the parity is not correct, then assuming that a character has been written to the utr, the transmission starts at 13 etu (the guard time gt must be programmed before transmitting). bit lct can be used for cards that are required to change from transmission to reception mode very fast. if lct is set high, then the uart automatically resets bits trn and lct at 10.85 etu if no parity error has occurred; the uart is ready to receive a character from the card at 12 etu (t = 0) or 11 etu (t = 1) after the previous start bit. if a parity error has occurred during transmission of the last character, then the uart stays in transmission mode with lct set, waiting for the software to rewrite the corrupted character.
2000 feb 21 20 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 handbook, full pagewidth mgr233 i/o trn p4 ff ff ff ff ff tbe lct r/w en int transmission read status start transmit read status int cleared write character anything buffer empty int cleared write character anything buffer empty start receive trn/lct reset set lct start transmit fig.9 character transmission with or without lct. s ynchronous cards if bit san (synchronous/asynchronous-n) is set, the software can operate with synchronous cards; the information available on the i/o line is copied on data bit 0 of the data bus without entering the uart when either registers sir or sor are selected. at the end of a transmission in synchronous mode, it is necessary to switch back to synchronous reception mode by reading register sir. the synchronous clock may be controlled by selecting clk stop high or stop low. contacts c4 and c8 may be controlled by ports p34 and p35 (operation depends on synchronous card type). synchronous input register (sir; address 3; read only) when this register is selected, i/o is copied on data bit 0 (p40) and may be read by the controller. synchronous output register (sor; address 3; write only) when this register is selected, i/o is copied on data bit 0 (p40) on the falling edge of en.
2000 feb 21 21 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 handbook, full pagewidth mgr234 p4 p40 clk en i/o r/w ff ff read write fig.10 using synchronous cards. e xtra guard time between the transmission of two characters to the card, the iso 7816 uart automatically inserts a number of guard etus equal to the value, called gt, stored in the gtr, see table 10. for a gt of fah, for example, the value would be 1111 1010 reading from d7 to d0. a gt of ffh has a special status which means 0 etu when the protocol is t = 0 and - 1 etu when the protocol is t = 1 (reception and transmission is possible at 11 etu). table 10 guard time register (gtr; address 6; write only; all bits cleared after reset) d7 d6 d5 d4 d3 d2 d1 d0 guard time value (gt) n7 n6 n5 n4 n3 n2 n1 n0 n7n6n5n4 n3n2n1n0 uart receive and transmit registers uart receive register (urr; address 4; read only; all bits cleared after reset) d7 to d0 are the data bits received from the card. because the uart automatically converts the characters according to the convention recognized during ts, all characters in the urr are in direct convention. the received character is loaded in the urr 0.5 etu after the parity shift, i.e. 10.5 etu after the edge of the start bit. this overwrites the previous character which should have been read by the controller. the uart checks the parity of the received characters; if the parity is wrong, then bit pe is set in the status register at the same time as bit rbf (receive buffer full). in protocol t = 0, i/o is pulled low between 10.5 and 11.75 etu in case of error. characters may be received from the card every 12 etu, even after a transmission (see lct; table 9). in protocol t = 1, reception is possible at 11 etu.
2000 feb 21 22 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 uart transmit register (utr; address 4; write only; all bits cleared after reset) bits d7 to d0 are the data bits to be transmitted to the card. due to the automatic conversion performed by the uart according to the convention detected during ts, the controller must write the characters to send to the card in direct convention. the character to be sent may be written to the utr as soon as bit tbe (transmit buffer empty) is set in the status register. if writing to the ucr occurs after 12.5 etu + gt after the previous start bit, then the transmission starts on the rising edge of en during the write operation. if writing to the ucr occurs before 12.5 etu + gt after the previous start bit, the uart waits until 12.5 etu + gt after the previous start bit before starting the transmission. in protocol t = 0, if a parity error is signalled by the card, the previous character must be rewritten to the utr. the uart will then wait 13 etu after the start bit of the previous character before restarting the transmission. s tatus register and interrupts the iso 7816 uart reports its activity to the microcontroller through the uart status register, which acts upon the interrupt line int. all bits except for d5 generate an interrupt on int, if enabled, when they are set. d0, d2, d3, d4, d6 and d7 are cleared on the rising edge of en after a read operation of the usr. d1 is cleared when the data in the reception buffer has been read-out. d5 may be used to check the cards presence and also to determine the reason for an emergency deactivation during a cards session. in case of early answer (ea) or mute card (mc) during automatic atr processing, the card is not automatically deactivated. if enabled, an interrupt is generated, and the controller then decides to deactivate or not. table 11 uart status register (usr; address 5; read only; all bits cleared after reset except for d5) bit name description d0 tx buffer empty (tbe) this bit is set when the uart has ?nished transmitting the data written in the utr (at 10.8 etu) or on the rising edge of trn; it is reset on the rising edge of en during a read status operation d1 rx buffer full (rbf) this bit is set when the uart has ?nished receiving a character from the card (at 10.5 etu); it is reset on the falling edge of en during the read status operation d2 first start detect (fsd) this bit is set on the falling edge of the ?rst start bit if ss = 1; it is reset on the rising edge of en during a read status operation d3 parity error (pe) this bit is set when a parity error has been detected by the uart in transmission or in reception mode at the same time as tbe and rbf; it is reset on the rising edge of en during a read status operation d4 early answer (ea) this bit is set if a start bit has been detected on i/o between the 200 and 400 ?rst clk pulses when the uart is con?gured in automatic atr processing; it is reset on the rising edge of en during a read status operation d5 off this bit is set if the card is present and reset if the card is not present; if cmdvcc is set high, it may also be reset if a hardware problem causing an emergency deactivation sequence has occurred d6 off interrupt (offi) this bit is set when off state has changed; it is reset on the rising edge of en during a read status operation d7 mute card (mc) this bit is set if a card has not answered after 80200 clk pulses for versions c2 and c3 (90000 for version c1), when the iso 7816 uart is con?gured in automatic atr processing; it is reset on the rising edge of en during a read status operation
2000 feb 21 23 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 auxiliary ram (mar0, address c or d, write only; mar1, address e or f, write only; mrr, mwr, address 8 or 9, read/write; all bits cleared after reset) in order to store data, 1 kbyte of auxiliary ram may be accessed through the peripheral interface. the content of the ram is undefined after reset. note that only ad3, ad2 and ad1 must be programmed for addressing the ram register, allowing faster operations if needed. there are two methods to address this memory: random method: the low order address is written in mar0, and the high order address is written in mar1. a write operation to mwr will write the data at the preselected address on the falling edge of en, and a read operation to mrr will load to port p4 the data that is stored at the preselected address on the falling edge of en. sequential method: once low order and high order addresses are written in mar0 and mar1, every read or write operation to mrr or mwr will increment the address that is stored in mar0 and mar1. thus it is possible to read or write data strings within the auxiliary ram without rewriting the addresses between 2 data bytes. the auto-increment feature is operational on the whole length of the ram. in case of overflow, the count starts again at address 00h. output ports extension register (per, address 7, write only; all bits cleared after reset) in this register, the four low order bits control the activation of the card. the four high order bits d4, d5, d6 and d7 each control auxiliary 2 ma push-pull output ports, which can be used for any purpose (leds, control signals, etc.). the electrical state of a port is high if the bit is low, and low if the bit is high. the bits are cleared after reset making the ports high. activation sequence when the card is inactive, pins v cc , clk, rst and i/o are low, having low impedance with respect to gnd. the step-up converter is stopped. the i/o is configured in reception mode with a high impedance path to the iso 7816 uart. any spurious pulses from the card during power-up will have no effect until i/o is enabled. when requirements are fulfilled (correct voltage supply, card present, no hardware problems), the microcontroller may initiate an activation sequence by setting bit cmdvcc high (t 0 ). the step-up converter starts (t 1 ) v cc starts rising from 0 to 5 v or to 3 v with a controlled rise time of typically 0.16 v/ m s(t 2 ) i/o, contacts c4 and c8 buffers are enabled (t 3 ); integrated pull-up resistors of 10 k w are connected to v cc clk is sent to the card (t 4 ) rst buffer is enabled (t 5 ). in order to allow a precise count of clock pulses during atr in manual mode, a defined time window (t 3 /t 5 ) is opened where the clock may be sent to the card using rstin. beyond this window, rstin does not respond to a clock pulse, and only monitors the cards rst contact. in automatic mode (atren set high), rst is monitored by the tda8006, rstin is inactive and clk is output by the tda8006 at t 3 . rst is low. if the card has not responded within the period of 40100 clk pulses for versions c2 and c3 (45000 for version c1), rst is set high for a maximum of 40100 clk pulses for versions c2 and c3 (45000 for version c1). it is also possible to customize the activation sequence by keeping clk stop low with rstin low beyond t 5 , and then output clk using the clk configuration. the sequencer is clocked by 1 64 f int which gives a time interval t of typically 25 m s. thus t 1 =0to 1 64 t, t 2 =t 1 +t, t 3 =t 1 + 4t, t 4 =t 3 to t 5 and t 5 =t 1 + 7t.
2000 feb 21 24 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 handbook, full pagewidth mgr235 cmdvcc vup v cc i/o rstin clk rst t 0 t 1 t 2 t 3 t 4 t 5 (= t act ) at r fig.11 manual activation sequence using t3/t5. handbook, full pagewidth mgr236 cmdvcc atren vup v cc i/o clk rst t 0 t 1 t 2 t 3 t 5 (= t act ) at r note1 fig.12 automatic activation sequence. (1) clk = 45000 for version c1 or 40100 for versions c2 and c3.
2000 feb 21 25 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 deactivation sequence when the session has completed, the microcontroller sets cmdvcc low (t 10 ). the circuit then executes an automatic deactivation sequence: card reset (rst goes low) (t 11 ) clock is stopped (t 12 ) i/o goes low (t 13 ) v cc falls to 0 v with typically 0.16 v/ m s slew rate (t 14 ) the step-up converter is stopped and clk, rst, v cc and i/o become low impedance to gnd (t 15 ). t 11 =t 10 + 1 64 t, t 12 =t 11 + 1 2 t, t 13 =t 11 +t, t 14 =t 11 + 3 2 t, t 15 =t 11 + 5t. t de is the time that v cc requires to fall to less than 0.3 v. handbook, full pagewidth mgr237 cmdvcc rst i/o v cc clk vup t 10 t 11 t 12 t 13 t 14 t 15 t de fig.13 deactivation sequence. protection the main hardware fault conditions monitored by the circuit are: overcurrent on v cc short circuits between v cc and other contacts card take-off during transaction. when one of these problems is detected, the security logic block sets the off bit low which generates an interrupt warning the microcontroller and initiates an automatic deactivation of the contacts. when the deactivation has completed and cmdvcc has been set low, the off bit goes high, unless the problem was caused by a card extraction, in which case it remains low until a card is inserted.
2000 feb 21 26 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 handbook, full pagewidth mgr238 off cmdvcc rst i/o v cc clk fig.14 emergency deactivation sequence after v cc short circuited to ground. auxiliary contacts c4 and c8 the auxiliary contacts c4 and c8 are controlled by ports p34 and p35 through two identical pseudo-bidirectional i/o lines. in the idle state, port p34 is pulled high to v dd by an integrated 20 k w resistor and c4 is pulled high to v cc by an integrated 10 k w resistor. this allows operation with a v cc value of 3 v and a v dd value of 5 v. the first side on which a falling edge occurs becomes the master. an anti-latch circuit disables the detection of a falling edge on the other side, which becomes the slave. after a delay of approximately 200 ns (t d ), the n transistor on the slave side is turned on which transmits the 0 present on the master side. when the master side goes back to logic 1, the p transistor on the slave side is turned on during t d , and then both sides return to their idle states. the maximum frequency on the i/o lines is 1 mhz.
2000 feb 21 27 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 limiting values in accordance with the absolute maximum rating system (iec 134). handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. thermal characteristics symbol parameter conditions min. max. unit v dda analog supply voltage - 0.5 +6.5 v v ddd digital supply voltage - 0.5 +6.5 v v n1 all input voltages except s1, s2 and vup - 0.5 v dd + 0.5 v v n2 voltage on pins s1, s2 and vup - 0.5 +7.5 v i n1 dc current into xtal1, xtal2, p30/rxd, p31/txd, reset, p33/ int1, p36/ wr, p37/ rd, p00 to p07, p20 to p27, p10/t2, p11/t2ex, ea, ale, psen, cdelay, pres, inhib, clkout and test - 5+5ma i n3 dc current from or to pins s1, s2 and vup - 200 +200 ma i n6 dc current from or to k0 to k3 - 5+5ma i n7 dc current from or into pin alarm (according to option choice) see table 12 - 5+5ma p tot total power dissipation t amb = - 20 to +85 c qfp44 - 400 mw qfp64 - 500 mw t stg storage temperature - 55 +150 c t j junction temperature - 140 c v esd electrostatic discharge on pins i/o, v cc rst, clk, c4, c8 and pres - 6+6kv on other pins - 2+2kv symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air qfp64 51 k/w qfp44 64 k/w
2000 feb 21 28 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 characteristics v dd =5v; v ss =0v; t amb =25 c; for general purpose i/o ports refer to 80ce560 data sheet; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dda analog supply voltage 4.2 - 6.0 v v ddd digital supply voltage 4.2 - 6.0 v i dd(pd) supply current in power-down mode v dd = 5 v; card inactive; note 1 -- 250 m a i dd(sm) supply current in sleep mode card powered, microcontroller in power-down mode but with clock stopped; note 1 -- 1500 m a i dd(om) supply current operating mode i cc = 65 ma; f xtal = 20 mhz; f clk = 10 mhz; f osc = 20 mhz; f clkout = 20 mhz; 5 v card; notes 1 and 2 130 - 180 ma i cc = 65 ma; f xtal = 20 mhz; f clk = 10 mhz; f osc = 20 mhz; f clkout = 20 mhz; 3 v card; notes 1 and 2 65 - 90 ma unloaded; f xtal = 20 mhz; f clk = 5 mhz; f osc = 10 mhz; f clkout = 5 mhz; 5 v card; notes 1 and 2 1 - 6ma unloaded; f xtal = 20 mhz; f clk = 5 mhz; f osc = 10 mhz; f clkout = 5 mhz; 3 v card; notes 1 and 2 0.5 - 4ma v th(vdd) threshold voltage on v dd (falling) 3.6 - 3.95 v v hys(vthvdd) hysteresis on v th(vdd) 50 - 250 mv v th(cdelay) threshold voltage on pin cdelay - 1.38 - v v cdelay voltage on pin cdelay -- v dd v i cdelay output current at pin cdelay pin grounded (charge) -- 1 -m a v cdelay =v dd (discharge) - 2 - ma t w alarm pulse width c cdelay =10nf - 10 - ms alarm (open drain active high or low output) i oh high-level output current active low option; v oh =5v -- 10 m a v ol low-level output voltage active low option; i ol =2ma - 0.3 - +0.4 v i ol low-level output current active high option; v ol =0v --- 10 m a v oh high-level output voltage active high option; i oh = - 2ma v dd - 0.8 - v dd + 0.3 v
2000 feb 21 29 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 crystal oscillator f xtal crystal frequency 4 - 25 mhz f ext frequency of external signal applied on pin xtal1 0 - 25 mhz clkout f clkout frequency on pin clkout 0 - 25 mhz v ol low-level output voltage i ol =5ma -- 0.8 v v oh high-level output voltage i oh = - 5ma v dd - 1 -- v t o(r) output rise time c l =60pf -- 10 ns t o(f) output fall time c l =60pf -- 10 ns d duty factor c l =60pf 40 - 60 % step-up converter f int internal oscillation frequency 2 2.5 3 mhz v vup voltage on pin vup - 6.5 - v reset output to the card (pin rst) v o(rst) output voltage inactive mode; no load 0 - 0.1 v inactive mode; i o(rst) = 1 ma 0 - 0.3 v i o(rst) output current when inactive and pin grounded 0 -- 1ma v ol low-level output voltage i ol = 200 m a0 - 0.3 v v oh high-level output voltage i oh = - 200 m av cc - 0.7 - v cc v t r rise time c l =30pf -- 0.1 m s t f fall time c l =30pf -- 0.1 m s clock output to the card (pin clk) v o(clk) output voltage inactive mode; no load 0 - 0.1 v inactive mode; i o(clk) = 1 ma 0 - 0.3 v i o(clk) output current when inactive and pin grounded 0 -- 1ma v ol low-level output voltage i ol = 200 m a0 - 0.3 v v oh high-level output voltage i oh = - 200 m av cc - 0.5 - v cc v t r rise time c l =30pf -- 8ns t f fall time c l =30pf -- 8ns f clk clock frequency 1.25 mhz idle con?guration 1 1.25 1.5 mhz operational 0 - 10 mhz d duty factor c l =30pf 45 - 55 % sr slew rate (rise and fall) c l =30pf 0.2 -- v/ns symbol parameter conditions min. typ. max. unit
2000 feb 21 30 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 card supply voltage (pin v cc ); note 3 v o(vcc) card supply output voltage inactive no load 0 - 0.1 v i o(vcc) =1ma 0 - 0.3 v pin grounded 0 -- 1ma active i cc < 65 ma; 5 v card 4.75 5 5.25 v i cc < 65 ma; 3 v card 2.8 3 3.2 v current pulses of 40 nas with i cc < 200 ma; t < 400 ns; f < 20 mhz; 5 v card 4.6 - 5.4 v current pulses of 24 nas with i cc < 200 ma; t < 400 ns; f < 20 mhz; 3 v card 2.75 - 3.25 v i o(vcc) card supply output current from 0 to 3 or 5 v -- 65 ma v cc short circuited to gnd -- 250 ma i cc(sd) shutdown current at pin v cc -- 80 - ma sr slew rate up or down (capacitor = 100 to 300 nf) 0.10 0.16 0.22 v/ m s data line (pin i/o); note 4 v o(i/o) output voltage inactive no load 0 - 0.1 v i o(i/o) =1ma -- 0.3 v i o(i/o) output current inactive and pin grounded 0 -- 1ma v ol low-level output voltage i/o con?gured as output; i ol =1ma 0 - 0.3 v v oh high-level output voltage i/o con?gured as output; i oh < - 50 m a 0.8v cc - v cc + 0.25 v v il low-level input voltage i/o con?gured as input - 0.3 - +0.8 v v ih high-level input voltage i/o con?gured as input 1.5 - v cc v i il low-level input current v il =0 v --- 600 m a i lih high-level input leakage current v ih =v cc -- 20 m a t i(r) input rise time c l =30pf -- 1 m s t i(f) input fall time c l =30pf -- 1 m s t o(r) output rise time c l =30pf -- 0.1 m s t o(f) output fall time c l =30pf -- 0.1 m s r pu(int) internal pull-up resistance between i/o and v cc 81013k w symbol parameter conditions min. typ. max. unit
2000 feb 21 31 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 auxiliary card contacts (c4 and c8); note 5 v o(c4,c8) output voltage inactive no load 0 - 0.1 v i o(c4,c8) =1ma -- 0.3 v i o(c4,c8) output current inactive and pin grounded --- 1ma v ol low-level output voltage c4 or c8 con?gured as output; i ol =1ma 0 - 0.3 v v oh high-level output voltage c4 or c8 and i/o con?gured as output; i oh < - 50 m a 0.8v cc - v cc + 0.25 v v il low-level input voltage c4 or c8 con?gured as input - 0.3 - +0.8 v v ih high-level input voltage c4 or c8 con?gured as input 1.5 - v cc v i il low-level input current v il =0v --- 600 m a i lih high-level input leakage current v ih =v cc -- 20 m a t i(r) input rise time c l =30pf -- 1 m s t i(f) input fall time c l =30pf -- 1 m s t o(r) output rise time c l =30pf -- 0.1 m s t o(f) output fall time c l =30pf -- 0.1 m s t d delay between falling edge on p34 and c4 (or c4 and p34) -- 200 ns r pu(int) internal pull-up resistance between c4 and v cc and c8 and v cc 81013k w f (max) maximum frequency on c4 or c8 -- 1 mhz timing t act activation sequence duration -- 225 m s t de deactivation sequence duration -- 100 m s t 3(start) start of the window for sending clock to the card -- 130 m s t 5(end) end of the window for sending clock to the card 145 -- m s output ports from extension ( k0 to k3) v ol low-level output voltage i ol =2ma -- 0.4 v v oh high-level output voltage i oh = - 2ma v dd - 1 -- v symbol parameter conditions min. typ. max. unit
2000 feb 21 32 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 notes 1. i dd in all configurations include the current at pins v dd , v dda and v ddram . 2. values given for program executed from internal rom. current consumption may be higher if program is executed from external rom or if charges are present on i/o ports. 3. a ceramic multilayer capacitor having a minimum value of 100 nf with a low esr should be used to obtain these specifications. 4. the i/o line has an integrated 10 k w pull-up resistor at pin v cc . 5. pins c4 and c8 have integrated 10 k w pull-up resistors at pin v cc ; ports p34 and p35 have integrated 20 k w pull-up resistors at pin v dd . options table 12 options card presence input (pin pres) v il low-level input voltage -- 0.3v dd v v ih high-level input voltage 0.7v dd -- v i lil low-level input leakage current v i =0v -- 20 m a i lih high-level input leakage current v i =v dd -- 20 m a features options alarm active high active low presence active high active low movec protection on off symbol parameter conditions min. typ. max. unit
2000 feb 21 33 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... application information handbook, full pagewidth mgr239 34 reset 35 p10/t2 36 p11/t2ex 37 n.c. 38 p30/rxd 39 p31/txd 40 p33/int1 41 p36/wr 42 p37/rd 43 p20 44 22 21 20 19 18 17 16 15 14 13 12 p21 vup s2 v dda s1 agnd clk rst gndram v ddram n.c. n.c. 1 p22 2 p23 3 psen 4 ale 5 y2 xtal2 6 xtal1 7 ea 8 p03 9 p02 10 p01 11 33 32 31 30 29 28 27 26 25 24 23 p00 test alarm cdelay clkout pres v dd gnd c8 c4 i/o v cc tda8006ah card read unit reset rx tx 14.745 mhz c20 33 pf c21 33 pf c7 4.7 nf c14 100 nf c9 100 nf c4 100 nf c6 100 nf c5 100 nf c1 100 nf c10 47 pf v dd c2 100 nf c3 10 m f v dd v dd v dd c20 100 nf c21 33 m f v dd + 5 v gnd j1 j1 1 2 r2 100 k w r1 0 w c8 c7 c6 c5 c1i c2i c3i c4i k1 k2 c4 c3 c2 c1 c5i c6i c7i c8i fig.15 application diagram.
2000 feb 21 34 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 package outlines unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-2 mo-112 97-08-01 99-12-27 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 19 y c e h a 2 d z d a z e e v m a 1 64 52 51 33 32 20 x pin 1 index b p d h b p v m b w m w m 0 5 10 mm scale qfp64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot319-2 a max. 3.20
2000 feb 21 35 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
2000 feb 21 36 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 feb 21 37 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
2000 feb 21 38 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 notes
2000 feb 21 39 philips semiconductors product speci?cation multiprotocol ic card coupler tda8006 notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 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